1. Field of the Invention
The invention relates to a transistor and a method for fabricating the same, and more particularly to a transistor having a recess gate structure and a method for fabricating the same.
2. Description of the Related Art
As the degree of integration of semiconductor devices has rapidly increased, the width of gates of transistors forming the semiconductor device has gradually decreased. In order to facilitate this trend, the concentration of impurities at junction regions and channels has gradually increased and the intensity of the electric field between a source region and a drain region has gradually increased. Electrons accelerate between the source region and the drain region due to the increased intensity of the electric field, thus generating a large number of hot carriers attacking a gate insulating layer close to the drain region. The hot carriers deteriorate electrical characteristics of the semiconductor device. Particularly, in a semiconductor memory, such as a DRAM, a leakage current is generated due to the increase of the intensity of an electric field between a source region and a drain region, thus exerting a bad influence on the refresh characteristic, which is one of the more important characteristics of the DRAM.
In addition to the foregoing structural problems, methods for fabricating the semiconductor device have several problems, as follows. Since the distance between the source region and the drain region is reduced, a punch-through margin is gradually decreased, and thus, the method further requires ion implantation for stopping punch-through. Particularly, a method for fabricating the DRAM further requires planarization of a landing plug for improving the refresh characteristic. That is, additional steps, which do not directly relate to the operation of the semiconductor device, are required in the manufacturing process.
In order to suppress the generation of hot carriers, a method for forming source and drain regions having a lightly doped drain (LDD) structure is most widely used. When the semiconductor device employs the LDD structure, the intensity of an electrical field between the source region and the drain region is decreased, but the concentration of impurities at both ends of a channel region is relatively decreased and thereby the amount of current is simultaneously decreased, thus obstructing high-speed switching operation of the semiconductor device.
Accordingly, in order to assist the high-speed switching operation of the semiconductor device and prevent the degradation of the semiconductor device due to the hot carriers, the length of gates is increased. However, the increase of the length of the gates exerts a bad influence on the integration of the semiconductor device. Further, the increase of the length of channels reduces the saturation current of a drain.